1. Technical Field
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a synchronous semiconductor memory device.
2. Discussion of the Related Art
With the advance of complementary metal oxide semiconductor (CMOS) integrated circuit technology, an operating speed of an integrated circuit has been improved. In order to increase the operating speed of the integrated circuit, it is typically necessary to improve a clock signal used for driving the integrated circuit. This is accomplished by increasing a clock frequency of the clock signal. Among the problems that result due to increasing the clock signal's frequency, is a clock skew that occurs between an external clock signal and an internal clock signal. The resulting clock skew should be fixed because it can cause the integrated circuit to operate erroneously. Generally, a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit has been used to solve the clock skew. However, such circuits have a drawback in that a synchronization time is long. In order to solve this drawback, a synchronous mirror delay (SMD) circuit has been proposed. Existing SMD circuits generate an internal clock signal that is synchronized with an external clock signal in only two cycles.
Typical SMD circuits are disclosed in U.S. Pat. No. 6,060,920, entitled “MULTIPLEX SYNCHRONOUS DELAY CIRCUIT”, and U.S. Pat. No. 6,373,913, entitled “INTERNAL CLOCK SIGNAL GENERATOR INCLUDING CIRCUIT FOR ACCURATELY SYNCHRONIZING INTERNAL CLOCK SIGNAL WITH EXTERNAL CLOCK SIGNAL”.
While operating speeds semiconductor memory devices continue to be increased, an operating speed of test equipment for testing semiconductor memory devices has been lagging when compared to that of the semiconductor memory devices. As the operating speed of the semiconductor memory devices increases, a frequency range in which the semiconductor memory device operates is different than that of the existing test equipment. As shown in FIG. 1, although an operating frequency range of the test equipment is within a predefined synchronization range of a clock generating circuit, such as a SMD, PLL and DLL, contained in the semiconductor memory device, it is difficult to test the high-speed memory device in its operating environment because the operating frequency range of the test equipment is low.
Accordingly, there is a need for a device that allows for the testing of a semiconductor memory device in its operating environment at a high frequency range using test equipment having a lower frequency range.